MAX5965AEAX+【PDF 18/54 页】IC PSE CTRLR FOR POE 36SSOP

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Sheet目录43

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High-Power, Quad, Monolithic, PSE Controllers

for Power over Ethernet

18 ______________________________________________________________________________________

A valid PD has a 25k& discovery signature characteristic

as specified in the IEEE 802.3af/at standard. Table 1

shows the IEEE 802.3af/at specification for a PSE detect-

ing a valid PD signature. See the Typical Operating

Circuits and Figure 1a (Detection, Classification, and

Power-Up Port Sequence). The MAX5965A/MAX5965B

can probe and categorize different types of devices con-

nected to the port such as: a valid PD, an open circuit, a

low resistive load, a high resistive load, a high capacitive

load, a positive DC supply, or a negative DC supply.

During detection, the MAX5965A/MAX5965B keep the

external MOSFET off and force two probe voltages

through the DET_ input. The current through the DET_

input is measured as well as the voltage at OUT_. A

two-point slope measurement is used as specified by

the IEEE 802.3af standard to verify the device connect-

ed to the port. The MAX5965A/MAX5965B implement

appropriate settling times and a 100ms digital integra-

tion to reject 50Hz/60Hz power-line noise coupling.

An external diode, in series with the DET_ input, restricts

PD detection to the first quadrant as specified by the

IEEE 802.3af/at standard. To prevent damage to non-PD

devices, and to protect themselves from an output short

circuit, the MAX5965A/MAX5965B limit the current into

DET_ to less than 2mA maximum during PD detection.

In midspan mode, the MAX5965A/MAX5965B wait 2.2s

before attempting another detection cycle after every

failed detection. The first detection, however, happens

immediately after issuing the detection command.

High-Capacitance Detection

The CLC_EN bit in register R23h[5] enables the large

capacitor detection feature for legacy PD devices.

When CLC_EN = 1, the high-capacitance detection limit

is extended up to 150礔. CLC_EN = 0 is the default

condition for the normal capacitor size detection. See

Table 1 and the Register Map and Description section.

Table 1. PSE PI Detection Modes Electrical Requirement

(Table 33-2 of the IEEE 802.3af Standard)

PARAMETER

SYMBOL

MIN

MAX

UNITS

ADDITIONAL INFORMATION

Open-Circuit Voltage

In detection mode only

Short-Circuit Current

In detection mode only

Valid Test Voltage

VALID

2.8

Voltage Difference

Between Test Points

TEST

Time Between Any Two

Test Points

This timing implies a 500Hz maximum probing

frequency

Slew Rate

SLEW

0.1

V/祍

Accept Signature

Resistance

GOOD

26.5

Reject Signature

Resistance

BAD

< 15

> 33

Open-Circuit Resistance

OPEN

500

Accept Signature

Capacitance

GOOD

150

Reject Signature

Capacitance

BAD

礔

Signature Offset Voltage

Tolerance

2.0

Signature Offset Current

Tolerance

礎

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